Backside PCB thermography of the ET-SoC-1 — physics notes

AI Foundry. Written Fri 9 Oct 2026 (week 41). Numbers: model-output.txt; code: scripts/.

Verified chip facts (lab repo + public press)

Caveat for him: 570 mm² is weakly sourced in public. Esperanto never published a die area I could find; Tom's Hardware is the only press figure, and an Apr 2021 COOL Chips report explicitly said the die size was undisclosed. ±20% on die area changes nothing below.

The model

Frequency-domain (phasor) axisymmetric conduction, scripts/pcb_ac_model.py: heatsink (Robin) → TIM → Cu lid → TIM → die (0.78 mm Si) → bumps/underfill → package substrate (1.1 mm, k_z 0.8 / k_r 15) → BGA ball layer (0.4 mm, k_z 20 / k_r 0.5) → PCB (1.6 or 2.4 mm, k_z 0.3–6.7 by via density, k_r 8–40 by copper planes) → air (Robin). Solves (jωρc)T − ∇·(k∇T) = q on a 2-D r–z grid; f = 0 gives steady state.

Three independent cross-checks all agree: 1. PSF + 2-D convolution reproduces the direct axisymmetric solve to 1%. 2. Layer-by-layer analytic MTF exp(−L·sqrt(q²k_r/k_z + jωρc/k_z)) agrees with the numerical MTF within ~2× across a 200:1 attenuation (analytic_mtf_check.py). 3. The AC answer moves 3% across h_bot 5→60 W/m²K and domain radius 45→120 mm: the AC signal is purely local, so it does not depend on how the card sheds heat.

The three results that decide it

1. DC board fraction: 15–36% in the model (literature 5–20%). Varies with how well the board sheds heat; the lab's own 1.47 °C/W network with a 0.7–1.9 °C/W heatsink implies ~20–30%. It does not matter — the AC answer is independent of it (check 3 above).

2. Amplitude is not the limit. Back-surface AC amplitude, quadrant source, per watt of first harmonic, PCB 1.6 mm, k_z = 1: 97 mK/W at 0.05 Hz, 39 at 0.1, 1.5 at 0.5, 0.12 at 1 Hz. Lock-in floor at NETD 35 mK / 25 Hz is 0.57 mK per pixel at 300 s, 0.016 mK averaged over an 11 mm disk. Even 1 W over a quadrant at 0.5 Hz gives SNR ≈ 50; 20 W gives ~1000.

3. Spatial blur is the limit, and it is set by the copper planes. Contrast transfer (MTF) at the shire scale is 0.001–0.017 — a 60:1 to 1000:1 loss. Per-layer at 0.5 Hz, shire checkerboard (7.44 mm period): silicon keeps 0.58, package substrate keeps 0.146, the PCB keeps 0.055, balls and underfill ~1.0. The two anisotropic copper-bearing layers do all the damage: k_r/k_z ≈ 18–19, so lateral spreading beats vertical transport by sqrt(19) ≈ 4.4× in length. The copper that makes the board a good spreader is what erases the lateral detail.

Smallest spatial period transferred at >50% contrast: 69 mm at 0.05 Hz, 27 mm at 0.5 Hz, 19 mm at 1 Hz. Modelled FWHM of a point source on the back: 43 mm at 0.05 Hz, 15 mm at 0.5 Hz, 12 mm at 1 Hz.

3b. But high SNR buys part of the resolution back. The blur is a low-pass; it is not the same as being unable to localise. Two separate questions (discrimination.py):

• Discrimination — one shire at tile (4,4) vs the adjacent tile (4,3), 3.72 mm apart, 0.5 W: matched-filter SNR 375 at 0.1 Hz, 131 at 0.2 Hz, 16 at 0.5 Hz (300 s integration; ×2.45 at 1800 s). A known PSF plus SNR ~10³ localises one compact source far below its own 15–29 mm blur, exactly as centroid fitting does in localisation microscopy.
• Deconvolution — recovering a general 32-shire activity map: condition number 1.6×10³ (1 Hz) to 1.1×10⁴ (0.05 Hz); effective rank at 1000:1 dynamic range 21 of 32 at 0.1 Hz, 24 at 0.2 Hz. So even the full map is not hopeless, but it is an ill-conditioned inverse problem, and at the frequencies where conditioning is best the amplitude has collapsed.

Sweet spot is 0.1–0.2 Hz. Beyond it, systematics — PSF knowledge, the board's real lateral inhomogeneity (connectors, DRAM, plane cutouts), VRM leakage, fan convection — not physics, set the floor.

Practical items the model turned up

• The heatsink is irrelevant to the AC signal: 96.9 mK/W with a 0.5 °C/W sink, 95.1 with none. Leaving it on costs ~2%. Good news for the experiment.
• Dominant uncertainty is the package substrate's k_z: 0.4 → 3.0 moves the amplitude 3–13×. A frequency sweep measures it (below).
• Vinyl tape costs half the AC signal at 0.5 Hz (0.18 mm PVC, D ≈ 0.107 mm²/s → exp(−L/µ) = 0.50). Kapton 25 µm keeps 0.89; matte black paint 20 µm keeps 0.94; graphite spray 0.98. See coating_penalty.py. For lock-in, emissivity accuracy does not matter (a uniform error is a scale factor) and the phase image is emissivity-independent.
• The phase is the calibration-free observable. Modelled lag on the back vs the drive: 100° (13.9 s) at 0.02 Hz, 161° (4.5 s) at 0.1 Hz, 468° (1.3 s) at 1 Hz. Lag ≈ 431·sqrt(f) deg over 0.05–0.5 Hz, and the slope ∝ 1/sqrt(k_z), so the sweep discriminates the three via cases (~780 / 430 / 170 deg·Hz^−0.5).
• 🛑 The VRM will outshine the chip. A watt dissipated in the card's power stage reaches the back through the PCB alone (0.049 at 0.5 Hz) versus 0.0045 for a watt in the die — ~10× per watt — and at 88 W card power the VRM sheds ~9 W. Expect a ~100× brighter lock-in signature from the power stage, correlated with the same modulation. It sits 20–50 mm from the package centre against a 10–20 mm blur: separable, but must be masked and checked.
• Pin the clock and the fan. aifoundry3 is held at 600 MHz (a boot service latches its governor at 0 W TDP) — use it. A fan whose speed tracks temperature modulates convection on the board back at the excitation frequency; fix it or log it.
• Card availability (7 Oct): aifoundry2's card is out of service (ran away to 138 °C and dropped off the bus). In service: aifoundry3's card and aifoundry1's two.
• Real modulation depths from the lab's own measurements: a quarter of the cores ≈ 6.8 W of switching power, half ≈ 13.6 W, all 1,024 ≈ 20.4–27.2 W (findings/12-heat-management.md).

Where the model is weak

• Axisymmetric: a square package and a square shire grid are handled via equal-area disks and the 2-D PSF convolution, not natively. The convolution agreeing with the direct solve to 1% says this is not the limiting error.
• No vias modelled individually — via density enters only as an effective k_z. The true k_z under a 2,494-ball power-delivery field could exceed my "dense" 6.7 W/mK locally.
• Steady-state absolute rise is overestimated (the model's board is a disk in still air; a real card is 111 × 168–312 mm with forced flow). The DC fraction is bracketed; the AC result is independent.
• Constant properties, no radiation coupling between board and chassis, no DRAM or VRM sources.

Recommended first experiment — the board-back transfer function sweep

~45 min of card time, no purchase. Card: aifoundry3 (its boot service latches the governor at 0 W TDP, so the clock is pinned at 600 MHz — no DVFS confound; aifoundry2's card has been out of service since 7 Oct 16:46). Heatsink stays on (costs ~2% of the AC signal).

Camera at ~10 cm: 0.28 mm/px, FOV 72 × 54 mm, so the whole 45 mm package fits with margin. Clamp it, don't hand-hold. First run bare solder mask (ε ≈ 0.9 is plenty; lock-in needs no absolute emissivity). Baffle the fan's airflow off the board back without blocking card cooling.

Use 0.47, 0.19, 0.093, 0.047 and 0.023 Hz, not the round numbers — see the NUC-harmonic trap below. The predictions in the table change by under 10% at these offsets.

Drive: the existing heat-placement harness (tools/claims-v3/hp/, placements.json) on one quadrant — 8 shires / 256 minions of random-normal fp32 TensorFMA ≈ 6.8 W of switching power (lab's own figure), square wave at 50% duty → first harmonic 4.33 W. Five frequencies × 300 s, plus a 300 s unmodulated run for the noise floor.

Demodulate offline: fit sin/cos at the known f against the frame timestamps, using the harness's logged on/off transitions. No hardware sync — a few ms of skew is nothing at 0.5 Hz. Drop a ~2 s window around each shutter/NUC event.

Pass/fail: amplitude must fall ~200× from 0.02 to 0.5 Hz, and the lag must be linear in sqrt(f) with slope 430 deg·Hz^−0.5 (the three via cases predict ~780 / 430 / 170). The slope measures the stack's effective through-plane diffusivity with no calibration of any kind.

🛑 The one control that matters: repeat with the load on the OPPOSITE quadrant. The amplitude peak must move ~11 mm. If it does not move, you are imaging the VRM, not the chip.

At 0.02 Hz the on-die sensor in the heated quadrant should swing ~1 °C (the lab measured +0.5 to +1.3 °C), giving an end-to-end die→back calibration inside the same run.

If the P3 is not enough — ranked

1. A 640×480 camera or a macro lens: no help at all. The limit is a 10–20 mm thermal blur; the P3 already resolves 0.28 mm at 10 cm (and diffraction at 10 µm, f/1.0 gives ~0.27 mm object-side, matched to the pixel). It over-resolves by 40–70×.
2. A cooled MWIR camera: marginal. Lower NETD and a higher frame rate buy ~2–4× in amplitude, i.e. about one octave of modulation frequency, i.e. ~1.3× in blur. The signal is gone above ~1 Hz regardless, so the high frame rate is wasted. Not worth the money here.
3. A thermistor/thermocouple array on the back: better amplitude, same blur. µK-class with a bridge and lock-in, immune to emissivity, NUC, narcissus and airflow — but the blur is in the board, so still ~10 mm. A good fixed 4×4/6×6 instrument, not an imager.
4. Change the viewing side — the only thing that buys real resolution. Heatsink off, camera on the coated lid: the upward path keeps 0.71–0.86 of the amplitude at 0.1–0.5 Hz against 0.0045–0.089 downward (10–100× more signal). The copper lid still spreads, so the blur floor is µ_Cu: 8.5 mm at 0.5 Hz, 4.2 mm at 2 Hz, 2.7 mm at 5 Hz — about one shire. Cost: no heatsink means low power and short runs on a shared lab card. Delidding would reach µ_Si ≈ 2.1 mm at 5 Hz; destructive, not his card, don't.
5. 🛑 Cheapest and best: lock-in on the 35 on-die PVT sensors. They already sit at 3.72 mm pitch, one per shire — the exact resolution the board cannot deliver. The lab's blocker was the 1 °C readout step ("one shire's own sensor moved by less than the 1 °C readout step; about +0.5 °C was expected"). That step is not a floor. A uniform quantiser of step q has RMS error q/sqrt(12), so correlating a 10 Hz telemetry stream against a known modulation gives amplitude noise (q/sqrt(12))·sqrt(2/N): 0.017 °C after 60 s, 0.0075 °C after 300 s — 30–70× below the LSB. A Monte-Carlo with a truncating quantiser recovers a 0.2 °C swing as 0.203 °C after 300 s and a 0.05 °C swing as 0.042 °C (ondie_lockin.py; the MC is deterministic, so its sd is 0 and the small residual bias is a quantisation artefact that real sensor noise would dither away). The +0.5 °C the lab expected and could not see would have come out at SNR 30 in one minute. No camera, no emissivity prep, no tripod.

Camera-side facts (cross-checked against the parallel session's notes)

camera-streaming-mount.md in this folder settles the optics independently and we agree: I derived f ≈ 4.28 mm from the prompt's "0.28 mm/px at 10 cm"; that file derives f = 4.3 mm, 12 µm pitch from the vendor FOV. Same number twice.

Two points from the raw-format work that matter for lock-in:

• The raw field is 16-bit at 1/64 K = 15.6 mK per LSB, below the 35 mK NETD. So the readout quantiser is finer than the noise and never limits a lock-in measurement — and even if it were coarser, the same dither argument as the on-die sensors applies.
• 🛑 The shutter/NUC fires about every 90 s, and the round modulation frequencies are exactly its harmonics. The NUC's fundamental is 1/90 Hz = 0.0111 Hz, so its harmonics sit at n/90 Hz: 0.1 Hz = 9/90, 0.2 Hz = 18/90 and 0.5 Hz = 45/90 all land exactly on a NUC harmonic and the shutter step will alias straight into the lock-in bin. 0.05 Hz (4.5/90) and 0.02 Hz (1.8/90) are safe. Fix: pick deliberately incommensurate frequencies — 0.47, 0.19, 0.093, 0.047, 0.023 Hz — and also drop a window around each NUC event. It costs nothing and removes the risk. The interval is only approximately 90 s, so the coherence drifts rather than being exact, but there is no reason to rely on that. Verify on the unmodulated control run.
• Diffraction at λ = 10 µm, f/1.0: Airy radius 12.2 µm at the sensor ≈ 0.27 mm at the object at 10 cm — matched to the pixel. Both are ~40× finer than the 10–20 mm thermal blur.

Reconciliation with the project's own record (read after the model was built)

Prior gyroscope/lab pages change three of my recommendations. Doctrine: previous reports are sources.

1. 🛑 My "use aifoundry3" was wrong. aifoundry2's card came back in service today at 16:34 with a new two-fan 92 mm bracket: idle 51 °C at 23.2 W, 0.68 °C/W die-to-air, 8-min burst levelling at 63 °C, heaviest workload at 75 °C (9 Oct lab report). It is also the card whose back is reachable — mounted backwards on purpose, 85 mm clear to the CPU cooler. Use aifoundry2. But the new fans created a confound: at 51 °C idle and 63–75 °C loaded the die now straddles the governor's 65 °C threshold, so the clock will hunt 600↔800 MHz during the modulation and the drive will not be a clean square wave. Pin it (latch the governor with a 0 W TDP, as aifoundry3's boot service does) or the lock-in measures the governor, not the load.
2. 🛑 Lid-side imaging with the heatsink off is already ruled out. The 30 Sep page concluded: no, not at 600 MHz nor at the firmware's lowest 100 MHz — the power is mostly leakage, and a bare package is 4–12 °C/W in still air (2–7 with a fan). My own lid-side numbers independently reach the same place: even if it could run bare, the copper lid's own diffusion length (8.5 mm at 0.5 Hz, 2.7 mm at 5 Hz) means shire-scale needs a delidded die — exactly what that page says. Drop option 4; two independent routes agree.
3. ✅ My VRM warning is already confirmed by first light. The 12:16 P3 capture of a card's back shows the package footprint as one broad hot patch plus two smaller hot spots that look like power stages — in a single frame, no averaging. So the VRM is both real and spatially separable, which is the good case. Mask it and use it as a free reference signal.
4. ✅ "Shiny parts read cold" confirmed: every capacitor behind the chip reads as a pair of cold dots (metal end caps reflecting the room). The 1-mil Kapton he already has is the right fix and costs only 11% of the AC amplitude at 0.5 Hz — vinyl tape would cost 50%.

The open loop I think can be closed now

The hub's table says one shire "waits on Roman's firmware" for raw 12-bit sensor codes at 0.061 °C steps. It does not have to wait. Lock-in on the existing whole-degree stream resolves 0.017 °C after 60 s and 0.0075 °C after 300 s — already finer than a single raw 12-bit read. The +0.5 °C the 7 Oct run expected on one shire and could not see would come out at SNR ~30 in one minute of correlated averaging, with no firmware change at all. Raw codes would then push it to ~1 mK. This is the cheapest shire-scale result available and it needs nothing from anyone.

Two numbers to reconcile with the measurement

• The 26 Sep plan predicts 21–65 mK on the back for a 2 s burst every 24 s. For that stimulus (f = 0.0417 Hz, 8.3% duty → first harmonic 0.165 P) my model gives ~80–310 mK for a 6.8 W quadrant and ~0.6 K for a 27 W full-chip load — 2–10× more optimistic. The gap is within the honest uncertainty (the package substrate's k_z alone moves the answer 3–13×), and the frequency sweep settles it. Take 21 mK as the conservative floor and ~300 mK as the central expectation.
• The hub states the board spreads heat 9–20 mm; my independent model gives 12–29 mm FWHM over 0.05–1 Hz, and >50% contrast only for periods above 19–69 mm. Same conclusion, slightly more pessimistic. Both say: halves and quadrants, not shires.

One framing constraint nobody has flagged

The gap allows the lens at 30–65 mm, which is 0.072–0.17 mm/px — the 45 mm package spans 279–627 px against a 256-px sensor, so it overflows the frame at every reachable distance. He cannot frame the whole package from that gap, and the opposite-quadrant control needs the whole package.

The exact arithmetic: thin-lens FOV width W = array·(d − f)/f with array 3.072 mm and f = 4.3 mm, so framing 45 mm needs d = 45·4.3/3.072 + 4.3 = 67.3 mm. Available is the 85 mm gap less the camera's 17 mm body = 68 mm, and the parallel session's own working range tops out at ~65 mm. So it is critical to within a millimetre, and realistically it does not fit once the cable and a mount need clearance. Fixes, cheapest first: the first-surface mirror on the never-ordered list, folding the path sideways out of the gap; or move the card one slot farther from the CPU cooler; or shoot two overlapping halves and register them on fiducials (acceptable, since the opposite-quadrant control only needs the peak position, not one frame). Worth settling before the lock-in afternoon.

Weak but real check against first light

The 15:35 live view of the capacitor field behind the chip auto-scaled 36.4–42.1 °C with the card at idle (23.2 W, die 51 °C) — roughly 11–17 °C above a ~25 °C room. My model's DC peak at realistic boundary conditions is 1.44–1.58 K/W of die power, which for ~18 W of chip power predicts ~27 K above ambient: about 2× hot, in exactly the direction and magnitude I flagged (truncated domain, no forced air across the board back, no conduction into the bracket and PCIe connector). It is a weak check — the live view auto-scales to the in-frame min/max and the shiny capacitor caps bias it — but the sign and size are consistent, and none of the AC predictions depend on the DC solve.